1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more particularly, to a semiconductor integrated circuit that measures leakage currents flowing in transistors formed on a semiconductor substrate.
2. Description of the Related Art
Conventionally, there have been known various measuring devices for measuring a quality of a semiconductor integrated circuit formed on a semiconductor substrate (see Japanese Patent Application Laid-Open No. 11-101851). Japanese Patent Application Laid-Open No. 11-101851 discloses a delay time measuring circuit and a delay time measuring method for determining whether a semiconductor integrated circuit being tested is acceptable by measuring a transmission delay time in the semiconductor integrated circuit.
There has also been a known structure that restricts variations in transistor characteristics in the semiconductor integrated circuit by measuring a leakage current in the transistor of the semiconductor integrated circuit and controlling a source voltage and a substrate bias in the semiconductor integrated circuit based on the measurement result. To measure the quality of each transistor formed on the semiconductor substrate, four-terminal transistors may be provided as a process monitor on a chip dicing line. In this case, however, it is necessary to prepare a special-purpose external measuring device that is connected to the transistors on the dicing line and measures the quality of each transistor. With this method, there is another problem that it is difficult to detect the locations of the transistors, after chips are cut out.
As a transistor quality measuring method to counter those problems, there has been a method by which a monitor circuit is provided in the form of a ring oscillator or delay chain together with a semiconductor integrated circuit formed on each chip (disclosed by Tschanz, J. W., Narendra, S., Nair, R., and De, V., “Effectiveness of adaptive supply voltage and body bias for reducing impact of parameter variations in low power and high performance microprocessors”, IEEE Journal of Solid-State Circuits, May 2003, Volume 38, Issue 5, p.p. 826-829). In the transistor measuring device using ring oscillators disclosed by Tschanz, et al, however, the rise time and the fall time of n-MOS transistors and p-MOS transistors affect respectively. As a result, the characteristics of the n-MOS transistors cannot be detected separately from the characteristics of the p-MOS transistors.